Please use this identifier to cite or link to this item: http://theses.ncl.ac.uk/jspui/handle/10443/828
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dc.contributor.authorEllis, Martin Andrew-
dc.date.accessioned2010-06-28T12:47:49Z-
dc.date.available2010-06-28T12:47:49Z-
dc.date.issued2008-
dc.identifier.urihttp://hdl.handle.net/10443/828-
dc.descriptionPhD Thesisen_US
dc.description.abstractComputer architectures can use custom logic in addition to general pur- pose processors to improve performance for a variety of applications. The use of custom logic allows greater parallelism for some algorithms. While conventional CPUs typically operate on words, ne-grained custom logic can improve e ciency for many bit level operations. The commodi ca- tion of eld programmable devices, particularly FPGAs, has improved the viability of using custom logic in an architecture. This thesis introduces an approach to reasoning about the correctness of compilers that generate custom logic that can be synthesized to provide hardware acceleration for a given application. Compiler intermediate representations (IRs) and transformations that are relevant to genera- tion of custom logic are presented. Architectures may vary in the way that custom logic is incorporated, and suitable abstractions are used in order that the results apply to compilation for a variety of the design parameters that are introduced by the use of custom logic.en_US
dc.language.isoenen_US
dc.publisherNewcastle Universityen_US
dc.titleCorrect synthesis and integration of compiler-generated function unitsen_US
dc.typeThesisen_US
Appears in Collections:School of Computing Science

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