Improved Finite Control Set of Fast Model Predictive Control for Modular Multilevel Inverter

Abstract

The rising demand of energy is currently an inexorable trend. According to the database, a number of consulting firms concurred with the prediction of a potential energy crisis in the near future due to extreme climate and natural disasters, import and export regulations under Covid, and the rapid development of industries such as electric vehicles. In the meantime, the cost of renewable energy is lower than it was in the past, and in light of mounting environmental concerns, accelerating the building of the renewable energy industry has become the optimal solution. On the other hand, the challenges of grid connection become an impetus for the evolution of the power transmission system. Nowadays, modular multilevel converter based HVDC system has become more popular and has the most potential. In addition, MMC (modular multilevel converter) is normally used in medium/high voltage motor drive systems as well. Modular multilevel converter inherits the advantages of low filter cost, low output distortion, and easy redundancy, from the multilevel converter family. Additionally, due to modular design, MMCs have the widest range of operating voltage and the broadest applications. The commercialization of MMC is hindered by two factors: the difficulty in developing high-voltage DC circuit breakers and the extremely complex and difficult control schemes. This research project is focused on the challenges in control schemes: design constraints, sub-module capacitor voltage control, and circulating current control. A comparison has been made between the classical control scheme and the model predictive control scheme. A new MPC (model predictive control) approach has been presented, which releases the heavy computational complexity, and improves the performance of circulating current minimization while smoothing the capacitor voltage ripples to lower the switching frequency. In addition, throughout the hardware implementation procedure, the realization of the general sorting algorithm has been improved, accelerating the sorting time while decreasing hardware resource use. Both simulation and hardware evaluations have been performed on this approach. In this thesis, specific outcomes and results are presented.