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Title: Improvements to grid connected photovoltaic inverters
Authors: Abeyasekera, Tusitha Darshana
Issue Date: 2005
Publisher: Newcastle University
Abstract: This thesis presents investigations into issues of power quality and reliability of grid connected inverters and proposes improved topological and control solutions to improve performance and cost effectiveness of these systems. Synchronisation of inverters to the grid can be problematic in its operational reliability. Of all grid synchronisation techniques phase locked loop based method offers a simple, robust and flexible solution. However the conventional PLL approach is inherently difficult to tune, due to the influence of its parameters on loop dynamics, filtering properties and output waveform spectral purity. The improved PLL proposed in the thesis, relieves the tuning task by decoupling the effect of its loop parameters from performance characteristics. Inverter power quality issues are addressed beginning from sources of harmonic distortion, classified as intrinsic and extrinsic. A potential intrinsic source is a look-up table generated reference sinusoid accessed in non-uniform increments resulting in harmonic, inter-harmonic or subharmonic distortion. The effect is studied in detail with analytical derivations and experimental results. On the other hand, extrinsic distortions are mainly caused by the distorted grid voltage. The effect of inductor current feedback, output current feedback and capacitor current feedforward on harmonic impedance is studied. The combination of inductor current feedback and capacitor current feedforward demonstrates good disturbance rejection and damped load transient performance on a low power grid connected inverter. It is shown that by carefully selecting the feedforward coefficient, the structure of the control system could be varied between the feedback and feedforward schemes. Theoretical concepts are validated on a purpose built 50OW 3-level grid connected inverter controlled through a generalised controller board based on TMS320C31 DSP. Multi-level inverters are presented as a favourable topological alternative to H-bridge grid connected inverters at medium and high power levels. The effect of number of levels, topology and switching strategy on switching losses, spectral performance and cost is analysed. Simulation results reveal that Boolean manipulation of PWM signals can be used to re-distribute harmonic energy for common mode cancellation, resulting in low switching harmonic amplitudes. Such a scheme - Carrier anti-phase sine (CAS) PWM is proposed and used in the prototype 3-level inverter.
Description: PhD Thesis
Appears in Collections:School of Electrical, Electronic and Computer Engineering

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