Surface engineering for silicon carbide interface

Abstract

Silicon carbide technology has made a significant improvements in these recent years, with a range of different devices, such as diodes, junction field effect transistors (JFETs) and metaloxide-semiconductor field effect transistors (MOSFETs) becoming commercially viable. The availability of relatively large and high quality wafers of 4H-SiC for device development has facilitated exciting breakthroughs throughout the world. The application areas of 4H-SiC devices include extreme environments such as high power, high frequency, high temperatures as well as optoelectronics. SiC technology has became indispensable due to the increasing demands from industrial sectors including automotive, military and aerospace. One of the crucial challenges for 4H-SiC MOSFETs is to increase the channel mobility which is plagued by the high density of interface traps. Post oxidation annealing (POA) in nitrogen gas environment or nitridation has become a standard process for the fabrication of MOSFETs with acceptable channel mobility around 35 cm2 /Vs, only about 4 % of the bulk mobility. POA using phosphoryl chloride (POCl3) or phosphorus pentoxide (P2O5) sources converts SiO2 into phospho-silicate glass (PSG) and has succesfully improved the channel mobility by a factor of 3 in comparison to nitridation. However, PSG is a polar material that increases the instability of MOS devices characteristic especially at high temperatures. In this work, the effect of inclusion of phosphorus (at an atomic concentration below 1 %) on the high temperature characteristics (up to 300◦C) of the SiO2/SiC interface is investigated. Capacitance – voltage measurements taken over a range of frequencies have been utilized to extract parameters including flatband voltage, threshold voltage, effective oxide charge, and interface state density. The variation of these parameters with temperature has been investigated for bias sweeps in opposing directions and a comparison made between phosphorus doped and undoped oxides. At room temperature, the effective oxide charge for SiO2 may be reduced by the phosphorus termination of dangling bonds at the interface. However, at high temperatures, the effective charge in the phosphorus doped oxide remains unstable and effects such as flatband voltage shift and threshold voltage shift dominate the characteristics. The instability in these characteristics was found to result from the trapped charges in the oxide (±1012 cm−3 ) or near interface traps at the interface of the gate oxide and the semiconductor (1012 to 1013cm−2 eV−1 ). Hence, the performance enhancements observed for phosphorus doped oxides are not realised in devices operated at elevated temperatures. v The electrical characteristics of 4H-SiC CMOS capacitor and transistor structures have been compared to the recently developed inversion MOS capacitor structure. Parameters including the interface state density, flatband voltage, threshold voltage and effective charge have been acquired from C-V characteristics of MOS capacitors to assess the effectiveness of the fabrication process in realising high quality gate dielectrics for CMOS process. A maximum critical electric field, in excess of 9.5 MV/cm has been demonstrated by the MOS capacitors without sustaining any oxide breakdown. Whilst, the interface trap density extracted from the n-type MOS capacitor is strongly correlated with n-channel field effect mobility, the channel mobility in the p-channel data shows no correlation. The impact of elevated temperatures on device characteristics of MOS capacitors and MOSFETs were also investigated utilizing C-V and I-V measurements performed at temperatures up to 400 ◦C. The temperature dependence of the flatband voltage, effective oxide charge and interface state density for MOS capacitors and the field effect mobility, threshold voltage and substhreshold swing for MOSFETs was examined in this section to study the effect of different dielectric formation at elevated temperatures. Finally, for the first time, the characteristics of inversion MOS capacitors with different frequencies (10 kHz to 1 MHz) for n and p-type are reported. The correlation between inversion capacitance and field effect mobility at room and elevated temperatures are discussed as a new method to assess the quality of SiC/SiO2 interface. For the first time, the characteristics of 3D structures formed in silicon carbide for the realisation of ultra-high performance nanoscale transistors, based on the FinFET topology is investigated. C-V characteristics show evidence of a second flatband voltage, located at a higher bias than that seen for purely planar devices. Two distinct peaks in the conductance – voltage characteristics are observed, centered at the flatband voltages, where the peak located at high bias correlates with the behaviour of the sidewall area. This suggests that the chemical behaviour of the sidewalls differs from those of the (0001) wafer surface. The breakdown electric field of the dielectric film grown on the 3D structure is in excess of 3 MVcm−1 . It is demonstrated that 3D transistors (FinFETs) do not utilise the gate voltage range where the abnormal characteristics exist and so this work reports for the first time the possibility of high performance nanoscale transistors in silicon carbide that can operate at high temperatures.