Silicon carbide junction field effect transistor integrated circuits for hostile environments

Abstract

Silicon carbide (SiC), in particular its 4H polytype, has long been recognised as an appropriate semiconductor for producing hostile environment electronics due to its wide energy band gap, large chemical bond strength and high mechanical hardness. A strong research foundation has facilitated the development of numerous sensor structures capable of operating at high temperatures and in corrosive atmospheres. Front-end electronics suitable for in situ signal conditioning are however lacking. Junction field effect transistors (JFETs) circumvent the pitfalls of contemporary alternative SiC transistor variants and have been found to operate predictably and consistently under such extreme conditions. This thesis demonstrates for the first time the capability of producing the necessary stable and high-performance interface circuits from n-channel lateral depletion-mode (NLDM) JFETs. The temperature dependence of pertinent bulk 4H–SiC material parameters relevant for describing the operation of macroscopic JFETs were initially studied. An accurate phenomenological model was developed to account for the variation of the thermal equilibrium free carrier concentrations. The position of the electrochemical potential and the distribution of free electron energies were found to change markedly when conduction band nonparabolicity, higher energy intrinsic bands and extrinsic effects were accounted for. These in turn were found to influence the determination of p-n junction contact potentials. The worst case error introduced through use of the Boltzmann approximation when applied to the channel and gate regions of the JFETs under study, having nominal doping concentrations of 1 1017 cm􀀀3 and 2 1019 cm􀀀3, respectively, were approximately 0:1% and 2%, respectively. A set of efficient and well behaved closed form expressions were subsequently developed for the free carrier concentrations in the framework of the Joyce- Dixon approximation (JDA) which are ideally suited for use in circuit simulations. Expressions for the electron conductively effective mass and an appropriate weighting function for the momentum relaxation time were subsequently identified. While the conductivity effective mass along the basal plane remained almost independent of temperature the non-parabolic band dispersion in the direction of principle axis introduced a temperature variation of 19% and 21% between 25 C and 400 C in the first and second conduction bands, respectively. Monolithically integrated 4H–SiC signal-level homo-epitaxial NLDM JFETs, p-n junction diodes and resistors were electrically characterised between room temperature and 400 C and their static and dynamic properties studied. Their behaviours were found to be well represented by macroscopic drift-diffusion models and were in agreement with predictions based on the bulk material properties. The intrinsic voltage gain of the fabricated JFET structures with nominal 9 μm gate length, 300nm channel depth and 250 μm gate width, under typical bias conditions, was roughly 100. As a consequence of the finite doping concentration in the buffer layer beneath the active device channel, with an experimentally determined value of approximately 3 1015 cm􀀀3, the devices under study were found to exhibit a strong body-effect. The thermal performance of the utilised tungsten capped annealed nickel-titanium and aluminium-titanium contacts, on highly doped n- and p-type regions, respectively, were investigated and appropriate methods for their characterisation described. The lowest recorded value of specific contact resistance was 1:90(50) 10􀀀5 cm2 with a corresponding sheet resistance of 7:89(9) 102 = . Lateral current flow through the contact side wall and the difference in sheet resistance under the contact were found to increase the value of the specific contact resistance determined from transfer length method (TLM) test structures by as much as 10% for n-type contacts. While exhibiting much larger contact resistance, the p-type contacts were found to have negligible impact on device performance due to the high impedance of the gate-channel and body-channel p-n junctions under typical operation. Physics based, Simulation Program with Integrated Circuit Emphasis (SPICE) compatible, integrated circuit (IC) consistent compact models were developed that are congruent with experimental measurements over the aforementioned range of temperature and across all essential bias levels. Most notably, a self-contained, asymmetric double-gated, non-selfaligned JFET model was developed that accurately accounts for the body-effect, voltage dependent mobility and temperature. An accurate yet efficient solver of the charge neutrality equation within each region of the device is utilised to account for incomplete ionisation of dopants and the temperature dependence of the p-n junction contact potentials. Meticulous agreement with experimental measurements was attained from a minimal number of input parameters. The modelled devices were used to simulate pertinent IC building blocks, including single stage and differential amplifiers, level-shifters and voltage buffers. The finite bodytransconductance of active load transistors were identified as a major degrading factor for the voltage gain. Practical methods to circumvent this are discussed with the aid of appropriate small-signal equivalent models. Finally, a design was presented for a two-stage 4H–SiC operational amplifier (op-amp) with direct current (DC) stability over the entire temperature range of study. Low-frequency small-signal voltage gains of 80 dB and 70 dB were achieved at 25 C and 400 C, respectively when utilising a 30V supply. A closed-loop non-inverting op-amp configuration with an ideal gain of 11 was then simulated and found to vary by just 1% between 25 C and 400 C. Such amplifiers are of great utility and form the cornerstone of numerous useful and important electronic systems.