Nanoscale strain characterisation of modern microelectronic devices

Abstract

Sources of stress and strain in modern microelectronics can be either beneficial to the electrical performance or detrimental to the mechanical integrity and ultimately lifetime of the device. Strain engineering is commonplace in state-of-the-art device fabrication as a means to boost performance in the face of device scaling limitation. The strain present in the device is directly related to the improvement factor and as such precise measurements and good understanding are of utmost importance due to the many thermal processing steps that can induce or cause relaxation of the strain. Front-end-of-line (FEOL) strain characterisation is becoming increasingly challenging due to the small volumes of material and nanoscale feature sizes being analysed. In this work, an extensive survey of strain characterisation techniques was undertaken. Narrow sSOI stripes were profiled using conventional Raman spectroscopy. Unlike with previous studies, it was shown that it is possible to achieve nanoscale measurements using current techniques. This study was supported by ANSYS FE simulation. The review of the literature briefly investigates the possibility of EBSD as a strain measurement tool. It is possible to calculate not just an absolute strain value as achievable with Raman spectroscopy, but the strain tensor. However, this is a difficult and complex process and not necessary for use in industry. This study proposes the possibility of a more simple method that would provide a good calibration technique to confirm Raman measurements. SERS and TERS are explored in detail as the most promising techniques when dealing with device scaling. Currently, SERS is a destructive technique not suitable for use in a highly cost driven industry such as semiconductor manufacturing. While it theoretically gives improved surface selectivity over conventional Raman spectroscopy, there is no improvement to the xy spatial resolution. With Si and SiGe samples, this study concludes there is also often no surface selectivity with either technique and the mechanisms behind the enhancement are not understood to the point of being able to implement the techniques in a process line. However, where a non-destructive technique is desired, outlined in this study is a method of achieving the SERS effect without sacrificing the sample. Aggressive scaling has forced the dimensions of the interconnecting wires that give the devices functionality to the deep submicron range. Copper, Cu has been introduced as a replacement to the traditionally used aluminium, Al because of its superior electrical and mechanical properties and scalability. However, as these wires begin to approach the dimensions of thin foils, the microtexture of the wires becomes significantly different from their bulk counterparts. This can affect the mechanical integrity of the interconnects and this has an impact on the reliability of the device. Failure mechanisms such as blistering, cracking and peeling caused by stress and strain are not uncommon and traditional methods of characterising residual stress in the thin films is no longer applicable to these narrow wires. The mechanical properties and microtexture of thin copper films annealed at temperatures comparative to those found in device manufacturing were characterised in some detail. EBSD was used to determine the grain size and structure of the films before nanoindentation confirmed properties such as hardness and elastic modulus. These results pave the way for investigation of strain applied along deep-submicron interconnects to lead to further understanding of what causes failure mechanisms from interconnecting wires.